China’s domestic accelerator shipments are increasing, but the number of chips sold is an imperfect guide to computing capacity delivered. Software compatibility, memory availability and interconnect performance all determine useful throughput. Recent reporting on continued chip shortages reinforces the distinction between manufacturing progress and the ability to run demanding workloads at scale.
Server DRAM procurement is not HBM qualification
Earlier attributed reporting described a substantial CXMT–Tencent server-memory supply relationship. Treat the reported procurement as distinct from a reviewed contract and do not infer that China’s HBM constraint is resolved.
1 OCTOBER 2026 · COMPUTE / MEMORY UPDATE
Software portability improves on Ascend while HBM scarcity remains unresolved.
DeepSeek’s Ascend-native DeepGEMM, DeepEP and FlashMLA components provide direct evidence that important training/inference primitives can be optimised for Ascend 950-class hardware with familiar APIs. Separately, Micron says the vast majority of its calendar-2027 HBM bit supply is already under agreement at materially higher pricing.
Interpretation: one part of the domestic-compute friction is improving at the software layer, but the memory constraint has not disappeared. The two developments reinforce the site’s system view: useful AI capacity depends on the interaction of accelerator, memory, interconnect and software rather than accelerator counts alone.
DeepSeek · DeepEP-Ascend ↗ · DeepGEMM-Ascend ↗ · Micron FY2026 results ↗
The role in the system
Accelerators, DRAM, HBM and the storage hierarchy.
Domestic manufacturing evidence improves, while the accelerator-memory constraint remains unresolved.
Companies in this layer
Huawei · Cambricon · Iluvatar · CXMT · YMTC
Names identify research roles, not a claim that every company has a partnership with every other company.
What would strengthen the thesis?
Evidence of good-die yields, qualified HBM supply and usable throughput.
What would weaken it?
Technical progress that fails to improve usable output or economic returns; delays, costs or commercial friction that prevent the value test being met.
Architecture notes
Compute
Accelerator performance remains foundational, but China's architecture increasingly emphasises heterogeneous accelerators, SuperPods and scale. The open question is how much useful output system design can recover from component constraints.
Memory & data hierarchy
HBM is a genuine constraint. DDR pooling and workload-aware context/SSD tiers may mitigate capacity pressure, but do not abolish HBM bandwidth requirements.
Follow the evidence
22 SEPTEMBER 2026 · RESEARCH UPDATE
A second domestic chip roadmap to track
Alibaba’s V900 joins the domestic accelerator roadmap. Compare delivered throughput, software compatibility and availability before translating vendor claims into usable capacity.